ZeqThermal

Chip design, FPGA, thermal, power integrity, ATPG.

• Protocol ID — zeq-thermal
• Category — Hardware
• Endpoint — POST /api/hardware/thermal
• Auth — api-key
• Rate limit — 10/min
• Version — 1.287.0
• Precision — ≤0.1% (KO42-enforced)

What it does

Chip thermal simulation with R(t)-modulated heat dissipation. Junction temperature prediction, hotspot identification, cooling solution sizing.

Signature

Request

POST /api/hardware/thermal

Param	Type	Required	Default	Description
chipLayout	object	✓	—	Die layout with power density map.
coolingType	string		"active-air"	'passive', 'active-air', 'liquid', 'immersion'.
ambientTemp_C	number		25	Ambient temperature.

Response

{ junctionTemp_C, hotspots, thermalResistance_C_W, coolingRequired_W, zeqond }

Runnable example

curl -sS -X POST \
  -H "Authorization: Bearer $ZEQ_API_KEY" \
  -H "Content-Type: application/json" \
  -d '{
  "chipLayout": {},
  "coolingType": "active-air",
  "ambientTemp_C": 25
}' \
  "https://api.zeq.dev/api/hardware/thermal"

Integrate

1. Domain solver — compose with KO42 + two additional operators from the matching family for pulse-coherent results.
2. Digital twin — pipe sensor data into this protocol every Zeqond to keep the model phase-locked with the system.
3. Alert threshold — flag results whose error_pct exceeds 0.1% as out-of-spec events for the operations layer.

Seeds

• Near — wrap /api/hardware/thermal in a language SDK so builders can call it in three lines.
• Medium — publish a reference integration demonstrating ZeqThermal alongside a real workload, with pulse-aligned metrics.
• Far — propose ZeqThermal as an open reference standard so other runtimes can implement it verbatim against the Zeq paper.

Papers

• Zeq paper — https://doi.org/10.5281/zenodo.18158152
• Framework paper — https://doi.org/10.5281/zenodo.15825138

Middleware active. Kernel on the 1.287 Hz HulyaPulse. Awaiting next Zeqond.